 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| PROTECTION PRODUCTS Description RailClamps are surge rated diode arrays designed to protect high speed data interfaces. The SR series has been specifically designed to protect sensitive components which are connected to data and transmission lines from overvoltage caused by ESD (electrostatic discharge), EFT (electrical fast transients), and tertiary lightning. The unique design of the SR series devices incorporates four surge rated, low capacitance steering diodes and a TVS diode in a single package. The TVS diode is constructed using Semtech's proprietary low voltage EPD technology for superior electrical characteristics at 3.3 volts. During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground. The internal TVS diode prevents over-voltage on the power line, protecting any downstream components. The low capacitance array configuration allows the user to protect two high-speed data or transmission lines. The low inductance construction minimizes voltage overshoot during high current surges. RailClamp Low Capacitance TVS Diode Array PRELIMINARY Features ! ESD protection to IEC 61000-4-2, Level 4 ! Array of surge rated diodes with internal ! ! ! ! ! ! ! ! ! EPD TVS diode Protects two I/O lines Low capacitance (<10pF) for high-speed interfaces Low leakage current (< 1A) Low operating voltage: 3.3V Solid-state technology SR3.3 Mechanical Characteristics JEDEC SOT-143 package Molding compound flammability rating: UL 94V-0 Marking : R3.3 Packaging : Tape and Reel per EIA 481 Applications ! ! ! ! ! ! Data and I/O lines Sensitive Analog Inputs Video Line Protection Portable Electronics Microcontroller Input Protection WAN/LAN Equipment Circuit Diagram Pin 4 Schematic & PIN Configuration 4 1 Pin 2 Pin 3 2 3 Pin 1 SOT-143 (Top View) Revision 9/2000 1 www.semtech.com SR3.3 PROTECTION PRODUCTS Absolute Maximum Rating R ating Peak Pulse Power (tp = 8/20s) Peak Pulse Current (tp = 8/20s) Peak Forward Voltage (IF = 1A, tp=8/20s) Lead Soldering Temperature Operating Temperature Storage Temperature Symbol Pp k IP P VFP TL TJ TSTG Value 150 10 1.5 260 (10 sec.) -55 to +125 -55 to +150 PRELIMINARY Units Watts A V C C C Electrical Characteristics SR 3.3 Par ame te r Reverse Stand-Off Voltage Punch-Through Voltage Snap -Back Voltage Reverse Leakage Current Clamp ing Voltage Clamp ing Voltage Maximum Peak Pulse Current Junction Cap acitance Symbo l VRWM V PT VSB IR VC VC IP P Cj IPT = 2 A ISB = 50mA VRWM = 3.3V, T=25C IPP = 1A, tp = 8/20 s IPP = 10A, tp = 8/20 s tp = 8/20 s Between I/O p ins and Gnd VR = 0V, f = 1MHz Between I/O p ins VR = 0V, f = 1MHz 6 3.5 2.8 1 7 15 10 10 Co nditio ns Minimum Typical Maximum 3.3 Units V V V A V V A pF 3 pF 2000 Semtech Corp. 2 www.semtech.com SR3.3 PROTECTION PRODUCTS Typical Characteristics Non-Repetitive Peak Pulse Power vs. Pulse Time 10 Peak Pulse Power - PPP (kW) 110 100 % of Rated Power or PP I 90 80 70 60 50 40 30 20 10 0.01 0.1 1 10 Pulse Duration - tp (s) 100 1000 0 0 25 50 75 100 125 150 Ambient Temperature - TA (oC) PRELIMINARY Power Derating Curve 1 0.1 Pulse Waveform 110 100 90 80 Percent of IPP 70 60 50 40 30 20 10 0 0 5 10 15 Time (s) 20 25 30 td = IPP/2 e -t Clamping Voltage vs. Peak Pulse Current 16 Waveform Parameters: tr = 8s td = 20s Line-To-Line 14 Clamping Voltage (V) 12 10 8 6 4 2 0 0 2 4 6 8 Line-To-Ground 10 12 Peak Pulse Current (A) Forward Voltage vs. Forward Current 10 9 Forward Voltage - VF (V) 8 7 6 5 4 3 2 1 0 0 5 10 15 20 25 30 35 40 45 50 Forward Current - I F (A) Waveform Parameters: tr = 8s td = 20s 2000 Semtech Corp. 3 www.semtech.com SR3.3 PROTECTION PRODUCTS Applications Information Device Connection Options for Protection of Tw o High-Speed Data Lines The SR3.3 TVS is designed to protect two data lines from transient over-voltages by clamping them to a fixed reference. When the voltage on the protected line exceeds the reference voltage (plus diode VF) the steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. Data lines are connected at pins 2 and 3. The negative reference (REF1) is connected at pin 1. This pin should be connected directly to a ground plane on the board for best results. The path length is kept as short as possible to minimize parasitic inductance. The positive reference (REF2) is connected at pin 4. The options for connecting the positive reference are as follows: 1. To protect data lines and the power line, connect pin 4 directly to the positive supply rail (VCC). In this configuration the data lines are referenced to the supply voltage. The internal TVS diode prevents over-voltage on the supply rail. 2. The SR3.3 can be isolated from the power supply by adding a series resistor between pin 4 and VCC. A value of 10k is recommended. The internal TVS and steering diodes remain biased, providing the advantage of lower capacitance. 3. In applications where no positive supply reference is available, or complete supply isolation is desired, the internal TVS may be used as the reference. In this case, pin 4 is not connected. The steering diodes will begin to conduct when the voltage on the protected line exceeds the working voltage of the TVS (plus one diode drop). Board Layout Considerations for ESD Protection Board layout plays an important role in the suppression of extremely fast rise-time ESD transients. Recall that the voltage developed across an inductive load is proportional to the time rate of change of current through the load (V = L di/dt). The total clamping voltage seen by the protected load will be the sum of PRELIMINARY Data Line and Power Supply Protection Using Vcc as reference Data Line Protection with Bias and Power Supply Isolation Resistor Pro Internal Data Line Pr o t ection Using Int ernal T V S Diode as Reference 2000 Semtech Corp. 4 www.semtech.com SR3.3 PROTECTION PRODUCTS Applications Information (continued) the TVS clamping voltage and the voltage due to the parasitic inductance (VC(TOT) = VC + L di/dt) . Parasitic inductance in the protection path can result in significant voltage overshoot, reducing the effectiveness of the suppression circuit. An ESD induced transient for example reaches a peak in approximately 1ns. For a PIN Descriptions 30A pulse (per IEC 61000-4-2 Level 4), 1nH of series inductance will increase the effective clamping voltage by 30V (V = 1x10-9 (30/1x10-9)). For maximum effectiveness, the following board layout guidelines are recommended: " " " I PP PRELIMINARY I SB I PT VBRR IR VRWM VSB VPT VC I BRR Minimize the path length between the SR3.3 and the protected line. Place the SR3.3 near the RJ45 connector to restrict transient coupling in nearby traces. Minimize the path length (inductance) between the RJ45 connector and the SR3.3. Figure 1 - EPD TVS IV Characteristic Curve The IV characteristic curve of the EPD device is shown in Figure 1. The device represents a high impedance to the circuit up to the working voltage (VRWM). During a transient event, the device will begin to conduct as it is biased in the reverse direction. When the punchthrough voltage (VPT) is exceeded, the device enters a low impedance state, diverting the transient current away from the protected circuit. When the device is conducting current, it will exhibit a slight "snap-back" or negative resistance characteristic due to its structure. This must be considered when connecting the device to a power supply rail. To return to a non-conducting state, the current through the device must fall below the snap-back current (approximately < 50mA). EPD TVS Characteristics The internal TVS of the SR3.3 is constructed using Semtech's proprietary EPD technology. The structure of the EPD TVS is vastly different from the traditional pn-junction devices. At voltages below 5V, high leakage current and junction capacitance render conventional avalanche technology impractical for most applications. However, by utilizing the EPD technology, the SR3.3 can effectively operate at 3.3V while maintaining excellent electrical characteristics. The EPD TVS employs a complex nppn structure in contrast to the pn structure normally found in traditional silicon-avalanche TVS diodes. The EPD mechanism is achieved by engineering the center region of the device such that the reverse biased junction does not avalanche, but will "punch-through" to a conducting state. This structure results in a device with superior dc electrical parameters at low voltages while maintaining the capability to absorb high transient currents. 2000 Semtech Corp. 5 www.semtech.com SR3.3 PROTECTION PRODUCTS Outline Drawing - SOT-143 PRELIMINARY Notes: (1) Controlling dimension: Inch (unless otherwise specified). (2) Dimension A and B do not include mold protrusions. Mold protrusions are .006" max. Land Pattern - SOT-143 2000 Semtech Corp. 6 www.semtech.com SR3.3 PROTECTION PRODUCTS Marking Codes Part Number SR3.3 Marking Code R3.3 PRELIMINARY Ordering Information Par t Number SR3.3.TC SR3.3.TG Working Voltage 3.3V 3.3V Qty per Reel 3,000 10,000 R eel Size 7 Inch 13 Inch Contact Information Semtech Corporation Protection Products Division 652 Mitchell Rd., Newbury Park, CA 91320 Phone: (805)498-2111 FAX (805)498-3804 2000 Semtech Corp. 7 www.semtech.com |
Price & Availability of SR33TC
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |